Staff Physical Design Engineer

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space-constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

About the Role

EnCharge AI is looking for a highly motivated and experienced Staff Physical Design Engineer to drive the physical implementation of our next-generation semiconductor chips. In this role, you will play a critical part in translating complex microarchitectures into high-performance, power-efficient silicon. Working closely with cross-functional teams, you will own block-level and top-level implementation using industry-standard EDA tools, tackle complex timing closure and power challenges, and guide designs all the way from netlist to successful foundry tapeout.

Key Responsibilities

• Drive block-level and top-level physical design, including floor-planning, placement, clock tree synthesis (CTS), and routing.
• Achieve aggressive timing, power, and area (PPA) targets through advanced timing closure techniques.
• Perform power grid verification and manage electromigration and IR drop (EM/IR) analysis and resolution.
• Develop and maintain automation scripts (Tcl/Python) to streamline design flows and methodologies.
• Collaborate with physical verification and foundry teams to ensure design rule compliance and successful tapeout execution.

Qualifications and Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 10–15 years of dedicated experience in physical design.
• Strong understanding of EDA implementation flows with extensive experience using Cadence design tools.
• Deep understanding of static timing analysis (STA) concepts and advanced timing closure methodologies.
• Demonstrated success in top-level and block-level physical design, with hierarchical floorplanning expertise a strong plus.
• Proficiency in low-power design techniques, debugging, and EM/IR check resolution/power grid verification.
• Strong scripting skills in Tcl or Python for design flow automation.
• Solid understanding of advanced process nodes and physical verification requirements associated with routing.
• Experience with physical design methodology, flow setup, and advanced flow evaluations.
• Prior experience with PDK management or foundry tapeout processes is highly desirable.