DFT Engineer - Verification

The company is a startup building foundational technology to address performance, scalability, and resiliency challenges in large-scale AI data center clusters. Backed by top-tier VC firms and notable angel investors, the company is led by experienced builders and operators who have founded, scaled, and exited companies successfully.

Headquartered in Silicon Valley, the company operates across a mix of remote and on-site locations in the U.S. and Canada. The environment emphasizes fairness, growth support, and meaningful work with a focus on craftsmanship and collaboration.

What we need:

A Senior DFT Verification Engineer responsible for ensuring the functionality, correctness, and quality of ASIC DFT logic. This role involves building robust verification environments, executing coverage-driven verification plans, and collaborating with DFT design engineers and manufacturing engineers to deliver reliable silicon.

The ideal candidate has 5+ years of experience in digital design verification, with at least 2 years in DFT verification specifically. They must have deep hands-on experience with SystemVerilog, UVM (or similar methodologies), and modern verification workflows. Knowledge of DFT topics such as scan/ATPG, JTAG, ijtag (ICL/PDL), boundary scan, MBIST, memory repair, and fuseboxes is required. Experience with gate-level simulation and tester pattern formats such as STIL is also necessary.

Key Responsibilities:

• Develop, implement, and maintain RTL verification environments using UVM or equivalent methodologies
• Create and execute coverage-driven verification plans aligned with design specifications
• Use EDA DFT tools (e.g., TestMax, Tessent) to create and run pre-silicon test cases for MBIST and scan fabric
• Develop directed test cases for non-vendor-supplied DFT logic to validate functionality and identify corner cases
• Assist in verifying ATPG patterns, especially at SOC level, along with manufacturing reset sequences
• Analyze simulation results, debug complex verification and design issues, and perform root-cause analysis in collaboration with DFT design engineers
• Implement and track functional and code coverage, driving verification to closure
• Develop reusable verification components and write SystemVerilog Assertions (SVA)
• Participate in design and verification reviews, providing input on design testability, correctness, and optimization
• Automate regression testing and enhance verification infrastructure using Python and scripting
• Contribute to continuous improvement of verification processes, tools, and methodologies
• Support post-silicon test bring-up debug along with DFT designers

Required Skills and Qualifications:

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
• 5+ years of experience in digital design verification, with at least 2 years in DFT verification
• Strong hands-on experience with UVM-based or similar verification methodologies
• Proficiency in SystemVerilog
• Experience in scripting (preferably Python) and automation
• Experience with industry-standard EDA tools (e.g., Synopsys VCS, Siemens/Mentor Questa, Cadence Xcelium)
• Experience with industry-standard EDA DFT tools (e.g., Synopsys TestMax + Yield Accelerator, Siemens Tessent)
• Solid understanding of digital design fundamentals
• Experience with verification of test sequences for high-speed PHY logic including PCIe and Ethernet (10G/40G/100G)
• Strong analytical and problem-solving skills
• Clear written and verbal communication skills for cross-functional collaboration
• High attention to detail and ability to deliver reliable, high-quality verification outcomes
• Ability to work independently and manage tasks to completion

Desired Skills:

• Experience with change control systems, especially git
• Experience verifying SoC-level designs